Welcome to Y86 Implementation using Logisim’s documentation!

This tutorial provides step-by-step instructions for CSCE312 term project. The goal of the term project is to implement Y86 64-bit sequential (non pipelined) architecture using Logisim digital logic design tool.

Contents

• Y86-86 Instruction Set Architecture
  • 1. Programmer Visible State
• Y86-86 Instruction Set Architecture
  • 1. Y86-64 Instructions
  • 2. Practice with Test Program (asum.ys)
• Logisim Memory File generation using yo file
  • 1. Overall Steps
  • 2. .yo file format
  • 3. Logisim Memory File
  • 4. YO2MEM pytyon script
• Timing of Y86-64 SEQ Stages
• Stage1: Instruction Fetch
  • Decoded instruction
  • PC increment
• Stage2: Decode and Write Back Stage
  • Decoding instruction and reading register value
  • Register file implementation
• Stage3: Execution Stage
  • Inputs
  • Outputs
  • Condition Code (CC) module
  • SetCC module
  • Cond module
• Stage4: Memory Stage
• Stage5: PC Update Stage

Indices and tables

• Index

• Module Index

• Search Page